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	Part Number	Hot Search : BTS140A MM3Z3V3 AS1337 WR06X473 B1608 1N980B 1N5821 IRF730AL
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8mx3aj www.icst.com/products/hiperclocks.html rev. b february 10, 2006 1 integrated circuit systems, inc. ics8m x 3 lvpecl c lock o scillator preliminary ics8m x 3 e lectrical s pecifications unless stated otherwise, v cc = 3.3v 5% or 2.5v 5%, t a = 0 c to +70 c (commercial), t a = -40 c to +85 c (industrial) m e t il o b m y s s n o i t a c i f i c e p s s n o i t i d n o c t s e t . n i m. p y t. x a ms t i n u s c i t s i r e t c a r a h c c d y l p p u s r e w o p v ( c c v , e e ) s n i p e g a t l o v y l p p u s r e w o pv c c 5 3 1 . 33 . 35 6 4 . 3v n o i t a r e p o v 3 . 3 5 7 3 . 25 . 25 2 6 . 2v ) y l n o 3 k m 8 d n a 3 j m 8 ( n o i t a r e p o v 5 . 2 t n e r r u c y l p p u s r e w o pi e e 5 7a mv = e o c c d e l b a s i d t u p t u o / w t n e r r u ci d e o 6 . 0 8mx3aj www.icst.com/products/hiperclocks.html rev. b february 10, 2006 2 integrated circuit systems, inc. ics8m x 3 lvpcecl c lock o scillator preliminary p arameter m easurement i nformation rms p hase j itter o utput r ise /f all t ime 3.3v o utput l oad ac t est c ircuit clock outputs 20% 80% 80% 20% t r t f v sw i n g pulse width t period t pw t period odc = out nout 2.5v o utput l oad ac t est c ircuit offset frequency f 1 f 2 phase noise plot rms jitter = area under offset frequency markers noise power o utput d uty c ycle /p ulse w idth /p eriod p in d escriptions r e b m u n e m a n e p y t n o i t p i r c s e d 1e ot u p n ip u l l u p . n i p e l b a n e t u p t u o . w o l n e h w e c n a d e p m i h g i h . s l e v e l e c a f r e t n i l t t v l / s o m c v l 2c nd e s u n u. t c e n n o c o n 3v e e r e w o p. n i p y l p p u s e v i t a g e n , 4 5 , t u o t u o n t u p t u o . s t u p t u o k c o l c l a i t n e r e f f i d . s l e v e l e c a f r e t n i l c e p v l 6v c c r e w o p. n i p y l p p u s r e w o p . s c i t s i r e t c a r a h c c d e e s , r o t s i s e r p u l l u p l a n r e t n i f o e u l a v l a c i p y t r o f m e t i l o b m y s n o i t i d n o c t i n u e g a t l o v t u p n iv i v o t 5 . 0 - c c 5 . 0 +v e g a t l o v t u p t u ov o v o t 5 . 0 - c c 5 . 0 +v e g a t l o v y l p p u s e v i t i s o pv c c 6 . 4v e c n e d e p m i l a m r e h t e g a k c a pd b t) m p f l 0 ( w / c e r u t a r e p m e t e g a r o t st s 0 0 1 + o t 0 4 -c e s u a c y a m s g n i t a r m u m i x a m e t u l o s b a r e d n u d e t s i l e s o h t d n o y e b s e s s e r t s s n o i t a c i f i c e p s s s e r t s e r a s g n i t a r e s e h t . e c i v e d e h t o t e g a m a d t n e n a m r e p s n o i t i d n o c y n a r o s n o i t i d n o c e s e h t t a t c u d o r p f o n o i t a r e p o l a n o i t c n u f . y l n o t o n s i s c i t s i r e t c a r a h c c a r o s c i t s i r e t c a r a h c c d n i d e t s i l e s o h t d n o y e b d e d n e t x e r o f s n o i t i d n o c g n i t a r m u m i x a m e t u l o s b a o t e r u s o p x e . d e i l p m i . y t i l i b a i l e r t c u d o r p t c e f f a y a m s d o i r e p a bsolute m aximum r atings scope qx nqx lvpecl 2v -1.3v 0.165v v ee v cc scope qx nqx lvpecl 2v -0.5v 0.125v v ee v cc
8mx3aj www.icst.com/products/hiperclocks.html rev. b february 10, 2006 3 integrated circuit systems, inc. ics8m x 3 lvpecl c lock o scillator preliminary a pplication i nformation t ermination for 3.3v lvpecl o utput the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance following outputs that gen- erate ecl/lvpecl compatible outputs. therefore, terminating re- sistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal dis- tortion. figures 1a and 1b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. f igure 1b. lvpecl o utput t ermination f igure 1a. lvpecl o utput t ermination v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin t ermination for 2.5v lvpecl o utput figure 2a and figure 2b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 to v cc - 2v. for v cc = 2.5v, the v cc - 2v is very close to ground level. the r3 in figure 2b can be eliminated and the termination is shown in figure 2c. f igure 2c. 2.5v lvpecl t ermination e xample f igure 2b. 2.5v lvpecl d river t ermination e xample f igure 2a. 2.5v lvpecl d river t ermination e xample r2 62.5 zo = 50 ohm r1 250 + - 2.5v 2,5v lvpecl driv er r4 62.5 r3 250 zo = 50 ohm 2.5v vcc=2.5v r1 50 r3 18 zo = 50 ohm zo = 50 ohm + - 2,5v lvpecl driv er vcc=2.5v 2.5v r2 50 2,5v lvpecl driv er vcc=2.5v r1 50 r2 50 2.5v zo = 50 ohm zo = 50 ohm + -
8mx3aj www.icst.com/products/hiperclocks.html rev. b february 10, 2006 4 integrated circuit systems, inc. ics8m x 3 lvpcecl c lock o scillator preliminary p ackage o utline - j s uffix for 6 l ead smt cerhermetic, 5mm x 7mm x 1.5mm a n b j (typ.) metalized c f (typ.) e (typ.) pin 1 index g (typ.) 6 terminal option pkg. d d 1 1 h (typ.) o 2 1 n s r e t e m i l l i m n i s n o i s n e m i d l o b m y sl a n i m o ne c n a r e l o t a 55 1 . 0 b 75 1 . 0 c 5 . 15 1 . 0 d 1 4 5 . 23 1 . 0 d 2 8 0 . 53 1 . 0 e 6 . 23 1 . 0 f 6 . 03 1 . 0 g 4 . 13 1 . 0 h . f e r 5 1 . 0- j . f e r 5 6 . 0- p art /o rder n umber i nformation part/order number: ics8m x 3 - fff.fff r p t u device supply voltage & frequency accuracy g = 3.3v 50 ppm h = 3.3v 100 ppm j = 2.5/3.3v 50 ppm k = 2.5/3.3v 100 ppm output type 3 = lvpecl output frequency (mhz) leading zeroes dropped. fourth decimal place added if necessary. consult ics for other frequencies. revision of product a = initial release package type (individual devices) j = 5x7mm ceramic smt ambient temperature range none = commercial = 0 c to +70 c i = industrial = -40 c to +85 c bulk packaging option none = tube t = tape and reel (1000 devices) note: lead-free by default (no addition "lf" code needed). (pb-free and rohs complaint)
8mx3aj www.icst.com/products/hiperclocks.html rev. b february 10, 2006 5 integrated circuit systems, inc. ics8m x 3 lvpecl c lock o scillator preliminary o rdering i nformation - 0c to + 70c (c ommercial ) while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extr aordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. the ics logo is a registered trademark, and hiperclocks is a trademark of integrated circuit systems, inc. all other trademarks are the property of their respective owners and may be registered in certain jurisdictions. o rdering i nformation - -40c to +85c (i ndustrial ) * r e b m u n r e d r o / t r a p* g n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t j a 0 0 0 . 5 7 - 3 x m 8 s c i3 x m 8 s c i0 0 0 . 5 7c i t e m r e h r e c d a e l 6e b u tc 0 7 o t c 0 t j a 0 0 0 . 5 7 - 3 x m 8 s c i3 x m 8 s c i0 0 0 . 5 7c i t e m r e h r e c d a e l 6l e e r & e p a t 0 0 0 1c 0 7 o t c 0 j a 0 0 0 . 0 0 1 - 3 x m 8 s c i3 x m 8 s c i0 0 0 . 0 0 1c i t e m r e h r e c d a e l 6e b u tc 0 7 o t c 0 t j a 0 0 0 . 0 0 1 - 3 x m 8 s c i3 x m 8 s c i0 0 0 . 0 0 1c i t e m r e h r e c d a e l 6l e e r & e p a t 0 0 0 1c 0 7 o t c 0 j a 0 5 2 . 6 0 1 - 3 x m 8 s c i0 5 2 . 6 0 1 3 x m 8 s c ic i t e m r e h r e c d a e l 6e b u tc 0 7 o t c 0 t j a 0 5 2 . 6 0 1 - 3 x m 8 s c i0 5 2 . 6 0 1 3 x m 8 s c ic i t e m r e h r e c d a e l 6l e e r & e p a t 0 0 0 1c 0 7 o t c 0 j a 0 0 0 . 5 2 1 - 3 x m 8 s c i0 0 0 . 5 2 1 3 x m 8 s c ic i t e m r e h r e c d a e l 6e b u tc 0 7 o t c 0 t j a 0 0 0 . 5 2 1 - 3 x m 8 s c i0 0 0 . 5 2 1 3 x m 8 s c ic i t e m r e h r e c d a e l 6l e e r & e p a t 0 0 0 1c 0 7 o t c 0 j a 0 5 2 . 6 5 1 - 3 x m 8 s c i0 5 2 . 6 5 1 3 x m 8 s c ic i t e m r e h r e c d a e l 6e b u tc 0 7 o t c 0 t j a 0 5 2 . 6 5 1 - 3 x m 8 s c i0 5 2 . 6 5 1 3 x m 8 s c ic i t e m r e h r e c d a e l 6l e e r & e p a t 0 0 0 1c 0 7 o t c 0 j a 5 7 3 . 9 5 1 - 3 x m 8 s c i5 7 3 . 9 5 1 3 x m 8 s c ic i t e m r e h r e c d a e l 6e b u tc 0 7 o t c 0 j a 5 7 3 . 9 5 1 - 3 x m 8 s c i5 7 3 . 9 5 1 3 x m 8 s c ic i t e m r e h r e c d a e l 6l e e r & e p a t 0 0 0 1c 0 7 o t c 0 j a 0 0 5 . 7 8 1 - 3 x m 8 s c i0 0 5 . 7 8 1 3 x m 8 s c ic i t e m r e h r e c d a e l 6e b u tc 0 7 o t c 0 t j a 0 0 5 . 7 8 1 - 3 x m 8 s c i0 0 5 . 7 8 1 3 x m 8 s c ic i t e m r e h r e c d a e l 6l e e r & e p a t 0 0 0 1c 0 7 o t c 0 j a 0 0 5 . 2 1 2 - 3 x m 8 s c i0 0 5 . 2 1 2 3 x m 8 s c ic i t e m r e h r e c d a e l 6e b u tc 0 7 o t c 0 t j a 0 0 5 . 2 1 2 - 3 x m 8 s c i0 0 5 . 2 1 2 3 x m 8 s c ic i t e m r e h r e c d a e l 6l e e r & e p a t 0 0 0 1c 0 7 o t c 0 j a 0 0 0 . 0 5 2 - 3 x m 8 s c i0 0 0 . 0 5 2 3 x m 8 s c ic i t e m r e h r e c d a e l 6e b u tc 0 7 o t c 0 t j a 0 0 0 . 0 5 2 - 3 x m 8 s c i0 0 0 . 0 5 2 3 x m 8 s c ic i t e m r e h r e c d a e l 6l e e r & e p a t 0 0 0 1c 0 7 o t c 0 j a 0 0 5 . 2 1 3 - 3 x m 8 s c i0 0 5 . 2 1 3 3 x m 8 s c ic i t e m r e h r e c d a e l 6e b u tc 0 7 o t c 0 t j a 0 0 5 . 2 1 3 - 3 x m 8 s c i0 0 5 . 2 1 3 3 x m 8 s c ic i t e m r e h r e c d a e l 6l e e r & e p a t 0 0 0 1c 0 7 o t c 0 e e s , d e i l p p a s i " x " e r e h w . n o i t a m r o f n i r e b m u n r e d r o / t r a p r o f 4 e g a p n o e l b a t e e s * y c a r u c c a y c n e u q e r f & e g a t l o v y l p p u s r e d r o / t r a p e h t n i . e l b a t n o i t a m r o f n i r e b m u n * r e b m u n r e d r o / t r a p* g n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t i j a 0 0 0 . 5 2 1 - 3 x m 8 s c i0 0 0 . 5 2 1 3 x m 8 s c ic i t e m r e h r e c d a e l 6e b u tc 5 8 o t c 0 4 - t i j a 0 0 0 . 5 2 1 - 3 x m 8 s c i0 0 0 . 5 2 1 3 x m 8 s c ic i t e m r e h r e c d a e l 6l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - i j a 0 0 5 . 2 1 2 - 3 x m 8 s c i0 0 5 . 2 1 2 3 x m 8 s c ic i t e m r e h r e c d a e l 6e b u tc 5 8 o t c 0 4 - t i j a 0 0 5 . 2 1 2 - 3 x m 8 s c i0 0 5 . 2 1 2 3 x m 8 s c ic i t e m r e h r e c d a e l 6l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - i j a 0 0 0 . 0 4 2 - 3 x m 8 s c i0 0 0 . 0 4 2 3 x m 8 s c ic i t e m r e h r e c d a e l 6e b u tc 5 8 o t c 0 4 - t i j a 0 0 0 . 0 4 2 - 3 x m 8 s c i0 0 0 . 0 4 2 3 x m 8 s c ic i t e m r e h r e c d a e l 6l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - i j a 6 2 3 . 9 6 6 - 3 x m 8 s c i6 2 3 . 9 6 6 3 x m 8 s c ic i t e m r e h r e c d a e l 6e b u tc 5 8 o t c 0 4 - t i j a 6 2 3 . 9 6 6 - 3 x m 8 s c i6 2 3 . 9 6 6 3 x m 8 s c ic i t e m r e h r e c d a e l 6l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - e e s , d e i l p p a s i " x " e r e h w . n o i t a m r o f n i r e b m u n r e d r o / t r a p r o f 4 e g a p n o e l b a t e e s * y c a r u c c a y c n e u q e r f & e g a t l o v y l p p u s r e d r o / t r a p e h t n i . e l b a t n o i t a m r o f n i r e b m u n

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